Interconnect Resistance Evolution Dependence on Material and Structure Dimensions

Jonathan Reid

Lam Research

Jonathan Reid has been a process development manager, principle engineer, and Fellow at Novellus Systems and Lam Research responsible for damascene copper electroplating process chemistry and hardware development used on the Sabre electroplating tool since 1996. Prior to joining Novellus Systems, he was employed at IBM from 1983 until 1996 and carried out process development in support in packaging, printed circuit board, and IC applications. Dr. Reid received a Ph.D. from the UNC Chapel Hill in 1983 and has published or presented over 100 papers and book chapters and has been issued over 100 US patents. 


Since the introduction of copper electroplating on TaN/Cu seed layers in 1998 dual damascene filling has combined with CVD tungsten contact metallization of contacts as the basis for virtually all integrated circuit interconnects. As the limits of these methods were reached, cobalt was introduced as a liner to enhance filling and then as a bulk conductor to replace both Cu and W. While these changes provided some extendibility of Cu interconnects, smaller dimensions will require more novel changes in the metallization process. New materials such as ruthenium and molybdenum, a reduction in the number of metal layer in a conductor, and sequences which replace dual damascene processing have been considered as extendibility directions.
This paper compares several alternatives for interconnect formation in <10nm dielectric="" openings="" and="" suggests="" preferred="" directions="" based="" on="" modeling="" of="" resistance="" reliability="" manufacturability="" considerations="" to="" characterize="" the="" circuit="" behavior="" numerous="" combinations="" conductor="" material="" barrier="" liner="" structure="" type="" a="" via-line="" segment="" was="" modeled="" as="" function="" opening="" using="" coventor="" semulator="" 3d="" aspect="" ratio="" both="" via="" trench="" segments="" held="" at="" 2="" 0="" for="" all="" feature="" dimensions="" br="">
Based on this modeling, the effects of barrier/ liner on reducing conductor volume, the effect of high resistivity of Cu alternatives, especially at larger feature dimensions, and a lack of manufacturable alternatives, lower metal level interconnects based on Cu lines combined with self-forming barrier/dielectric barrier could play a strong role in enabling 8-10nm conductors which do not exceed resistance targets for typical circuit designs.