Sophisticated Architecture for High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology


Dr Koji Sakui

Principal Scientist, IEEE Fellow
Tokyo Institute of Technology, IIR, The WOW Alliance, Yokohama, Japan

BIOGRAPHY
Honda Research Institute Japan Co., Ltd.
8-1 Honcho, Wako-shi, Saitama 351-0188, Japan
+81-80-4928-3582, e-mail: koji.sakui@jp.honda-ri.com

Koji Sakui received the B.Eng. and M.Eng. degrees, both in instrumental engineering, from Keio University in 1979 and 1981, respectively, and the Ph.D. degree from Tohoku University in 1995.

In 1981, he joined the Toshiba Research and Development Center, Toshiba Corporation, where he was engaged in the circuit design of DRAM’s. Since 1990 he has been engaged in the development of high density NAND Flash memories. From 1991 through 1993, he was a Visiting Scholar at Stanford University, doing research in the field of multi-chip module and BiCMOS technologies. He managed Flash Memory Design Department of SoC R & D Center to develop 90nm, 70nm, and 55nm NAND Flash memory design. He moved to Sony Corporation in December, 2004, and served as a General Manager of Memory System Department of System LSI Business Division, Semiconductor Business Group. In April, 2007, he moved to NAND Products Group, Intel Corporation, Folsom CA, where he was a Research Scientist. In April 2009, he became a Visiting Professor of Tohoku University. In June 2010, he joined Micron as Sr. Architect and Technologist – Memory Innovations, where he has 62 US granted patents on the 3D NAND. In December 2018, he has become a Principal Scientist of Honda Research Institute Japan. He served a part-time professor of Tsukuba University in 2013. Also, since 2009, he has been a part-time professor of Waseda University.

Dr. Sakui is a member of the IEEE Electron Device Society, and served a Memory Coordinator for ITC (International Test Conference) in 2001, and a Technical Program Committee for the IEEE NVSMW (Non-Volatile Semiconductor Memory Workshop), currently the IEEE IMW (International Memory Workshop) from 1998 to 2012. On January 1st, 2012, he became an IEEE Fellow, with the accompanying citation: “for the contribution to NAND flash memories.”

He holds 152 US patents granted, and published over 25 technical papers. He received Kanagawa Governor Patent Award in 1997 and Kanto District Patent Award in 2005.



ABSTRACT

This paper proposes a sophisticated architecture for the High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the bumpless TSV for the Wafer-on-Wafer (WOW) technology [1]-[2]. The bumpless interconnects technology can drastically increase the number of TSVs per chip, and reduce the impedance of the TSV interconnects. Therefore, a further higher speed and higher density HBM can be realized. Also, the High Bandwidth NAND (HBN), which can read and program by plane instead of by line by using the bumpless TSV, has been proposed [3]-[5].

References
[1] T. Ohba, “Three-Dimensional (3D) Integration Technology,” doi: 10.1149/1.3567707 ECS Trans. volume 34, issue 1, pp.1011-1016, 2011.
[2] T. Ohba, N. Maeda, H. Kitada, K. Fujimoto, A. Kawai, K. Arai, K. Suzuki, and T. Nakamura, IEICE Trans Electron., Electron. Soc. J93-C [11] p.464, 2010 in Japanese.
[3] K. Sakui and T. Ohba, “Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation,” in the IEEE CICC Dig. Tech. Papers, 22-6, April 2019.
[4] K. Sakui and T. Ohba, “Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation,” in the IEEE IMW Dig. Tech. Papers, pp.60-63, May 2019.
[5] K. Sakui and T. Ohba, “High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology,” in the IEEE 2019 International 3D Systems Integration Conference Dig. Tech. Papers, Paper Id: 3DIC2019.4005, Ocbober 2019.